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an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. production data. ADC141S628-Q1 snoi146c ? september 2011 ? revised december 2017 ADC141S628-Q1 14-bit, 200-ksps, pseudo-differential, micro-power adc 1 1 features 1 ? qualified for automotive applications ? aec-q100 qualified with the following results: ? device temperature grade 2: ? 40 c to 105 c ambient operating temperature range ? device hbm esd classification level h2 ? device cdm esd classification level c6 ? 14-bit resolution with no missing codes ? specified performance up to 200 ksps ? pseudo differential inputs ? zero-power track mode ? 150-mv swing around gnd on negative input ? separate digital i/o and analog supplies ? operating temperature range of ? 40 c to +105 c ? spi ? , qspi ? , microwire, dsp-compatible serial interface ? conversion rate: 50 ksps to 200 ksps ? inl ( ? 15 c to +65 c): 0.95 lsb (max) ? dnl: 0.95 lsb (max) ? post calibration tue ( ? 15 c to +65 c): 0.5 mv (max) ? snr: 80 dbc (min) ? thd: ? 97 dbc (typ) ? enob: 13.0 bits (min) ? power consumption: ? 200 ksps, 5 v: 4.8 mw (typ) ? power-down, 5 v: 13 w (typ) typical application diagram 2 applications ? automotive battery management ? automotive navigation ? portable systems ? medical instruments ? instrumentation and control systems ? motor control ? direct sensor interface 3 description the ADC141S628-Q1 device is a 14-bit, 200-ksps, pseudo-differential, analog-to-digital converter (adc) that is aec-q100 grade 2 qualified. the converter is based on a successive-approximation register (sar) architecture and has pseudo-differential analog inputs. the signal path is maintained from the internal sample-and-hold circuits throughout the adc to provide excellent common-mode noise rejection. the ADC141S628-Q1 features a zero-power track mode where the adc is consuming the minimum amount of supply current while the internal sampling capacitor tracks the applied analog input voltage. the serial data output of the ADC141S628-Q1 is straight binary and is compatible with several standards, such as spi, qspi, microwire, and many common dsp serial interfaces. the ADC141S628-Q1 has no latency which means the conversion result is clocked out by the serial clock input and is the result of the conversion currently in progress. the ADC141S628-Q1 can be operated with independent analog (va) and digital input/output (vio) supplies. va and vio can range from 4.5 v to 5.5 v and can be set independent of each other. this functionality allows a user to maximize performance and minimize power consumption. similarly, the ADC141S628-Q1 uses an external reference that can be varied from 1.0 v to va allowing users to optimize the full dynamic range of the input. the pseudo- differential input, low power consumption, and small size make the ADC141S628-Q1 ideal for remote data acquisition applications. operation is specified over the temperature range of ? 40 c to +105 c and clock rates of 0.36 mhz to 3.6 mhz. the ADC141S628-Q1 is available in a 10- lead package. device information (1) part number package body size (nom) ADC141S628-Q1 vssop (10) 3.00 mm 3.00 mm (1) for all available packages, see the orderable addendum at the end of the data sheet. productfolder 100 : + adc141s628 -q1 v ref +in - in gnd v a sclk d out csb 0.1 p f 10 p f 0.1 p f + 10 p f +5v controller lm4040 -4.1 v io support &community tools & software technical documents ordernow
2 ADC141S628-Q1 snoi146c ? september 2011 ? revised december 2017 www.ti.com product folder links: ADC141S628-Q1 submit documentation feedback copyright ? 2011 ? 2017, texas instruments incorporated table of contents 1 features .................................................................. 1 2 applications ........................................................... 1 3 description ............................................................. 1 4 revision history ..................................................... 2 5 pin configuration and functions ......................... 4 6 specifications ......................................................... 5 6.1 absolute maximum ratings ...................................... 5 6.2 esd ratings .............................................................. 5 6.3 recommended operating conditions (1) ................... 5 6.4 ADC141S628-Q1 converter electrical characteristics ........................................................... 6 6.5 ADC141S628-Q1 timing requirements ................... 8 6.6 typical characteristics ............................................ 10 7 detailed description ............................................ 14 7.1 overview ................................................................. 14 7.2 feature description ................................................. 14 7.3 device functional modes ........................................ 17 8 application and implementation ........................ 18 8.1 application information ............................................ 18 9 power supply recommendations ...................... 19 9.1 analog and digital power supplies ......................... 19 9.2 voltage reference .................................................. 19 10 layout ................................................................... 20 10.1 layout guidelines ................................................. 20 11 device and documentation support ................. 21 11.1 device support ...................................................... 21 11.2 documentation support ........................................ 22 11.3 receiving notification of documentation updates 22 11.4 community resources .......................................... 22 11.5 trademarks ........................................................... 22 11.6 electrostatic discharge caution ............................ 22 11.7 glossary ................................................................ 23 12 mechanical, packaging, and orderable information ........................................................... 23 4 revision history note: page numbers for previous revisions may differ from page numbers in the current version. changes from revision b (november 2017) to revision c page ? changed first features bullet, added aec-q100 qualification bullet and sub-bullets ............................................................ 1 ? changed ADC141S628-Q1 to ADC141S628-Q1 throughout document ................................................................................ 1 ? changed front page figure ..................................................................................................................................................... 1 changes from revision a (september 2011) to revision b page ? added device information table, pin configuration and functions section, esd ratings table, thermal information table, functional block diagram section, feature description section, device functional modes section, application and implementation section, power supply recommendations section, layout section, device and documentation support section, and mechanical, packaging, and orderable information section ................................................................ 1 ? changed msop to vssop throughout document ................................................................................................................ 1 ? changed pin out diagram title from connection diagram ................................................................................................... 1 ? deleted ordering information table ........................................................................................................................................ 4 ? added i/o column to pin functions table .............................................................................................................................. 4 ? added maximum specification to power consumption row of absolute maximum ratings table .......................................... 5 ? changed footnote 1 of absolute maximum ratings table ...................................................................................................... 5 ? changed operating ratings table title to recommended operating conditions ................................................................... 5 ? changed operating temperature range parameter specifications to min and max specifications from ? 40 t a 105 max specification ................................................................................................................................................................... 5 ? added f sclk parameter to recommended operating conditions from operating conditions section; deleted operating conditions section ................................................................................................................................................. 5 ? deleted package thermal resistance table ......................................................................................................................... 5 ? added unit to analog input pin, +in , analog input voltage , and digital input pins voltage range parameters ....................... 5 ? deleted footnote 1 from recommended operating conditions table and changed last footnote to include updated link ......................................................................................................................................................................................... 5 ? changed condition statement of ADC141S628-Q1 converter electrical characteristics table to remove boldface condition ................................................................................................................................................................................. 6 ? changed inl and pctue parameter specification test conditions ....................................................................................... 6
3 ADC141S628-Q1 www.ti.com snoi146c ? september 2011 ? revised december 2017 product folder links: ADC141S628-Q1 submit documentation feedback copyright ? 2011 ? 2017, texas instruments incorporated ? added t a = ? 40 c to +105 c to i dcl parameter test conditions ........................................................................................... 6 ? changed v a to max specification from typ specification in v ref parameter .......................................................................... 7 ? changed f sclk = 0 to f sclk = low in i va (pd), i vio (pd), and i vref (pd) parameter test conditions ......................................... 7 ? deleted last footnote from ADC141S628-Q1 converter electrical characteristics table ....................................................... 7 ? changed condition statement of ADC141S628-Q1 timing requirements table to remove boldface condition .................... 8 ? added temperature conditions to certain parameters in the ADC141S628-Q1 timing requirements table ......................... 8 ? changed title of typical characteristics from typical performance characteristics ........................................................... 10 ? changed overview title from functional description ........................................................................................................... 14 ? deleted last sentence of second paragraph in reference input (v ref ) section ................................................................... 14 ? changed last paragraph of reference input (v ref ) section ................................................................................................. 14 ? changed layout guidelines title from pcb layout and circuit considerations ................................................................... 20
4 ADC141S628-Q1 snoi146c ? september 2011 ? revised december 2017 www.ti.com product folder links: ADC141S628-Q1 submit documentation feedback copyright ? 2011 ? 2017, texas instruments incorporated 5 pin configuration and functions dgs package 10-pin vssop top view pin functions pin i/o description no. name 1 v ref reference input voltage reference input. a voltage reference between 1 v and v a must be applied to this input. v ref must be decoupled to gnd with a minimum ceramic capacitor value of 0.1 f. a bulk capacitor value of 1.0 f to 10 f in parallel with the 0.1- f capacitor is recommended for enhanced performance. 2 +in analog signal input, positive noninverting input. +in is the positive analog input for the signal applied to the ADC141S628-Q1. 3 ? in analog signal input, negative inverting input. must be gnd 150 mv. 4 gnd supply ground. gnd is the ground reference point for all signals applied to the ADC141S628-Q1. 5 gnd supply ground. gnd is the ground reference point for all signals applied to the ADC141S628-Q1. 6 cs digital input chip-select bar. cs must be active low during an spi conversion, which begins on the falling edge of cs. the ADC141S628-Q1 is in acquisition mode when cs is high. 7 d out digital output serial data output. the conversion result is provided on d out . the serial data output word is comprised of two null bits followed by 14 data bits (msb first). during a conversion, the data are output on the falling edges of sclk and are valid on the subsequent rising edges. 8 sclk digital input serial clock. sclk is used to control data transfer and serves as the conversion clock. 9 v io supply digital input/output power-supply input. a voltage source between 4.5 v and 5.5 v must be applied to this input. v io must be decoupled to gnd with a minimum ceramic capacitor value of 0.1 f. 10 v a supply analog power-supply input. a voltage source between 4.5 v and 5.5 v must be applied to this input. v a must be decoupled to gnd with a minimum ceramic capacitor value of 0.1 f. 1 23 4 5 6 7 8 9 10 sclk d out gnd - in +in cs v ref v a v io gnd
5 ADC141S628-Q1 www.ti.com snoi146c ? september 2011 ? revised december 2017 product folder links: ADC141S628-Q1 submit documentation feedback copyright ? 2011 ? 2017, texas instruments incorporated (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions . exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) all voltages are measured with respect to gnd = 0 v, unless otherwise specified. (3) when the input voltage (v in ) at any pin exceeds the power supplies (v in < gnd or v in > v a ), the current at that pin must be limited to 10 ma and v in must be within the absolute maximum rating for that pin. the 50-ma maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 ma to five. (4) the absolute maximum junction temperature (t j max) for this device is 150 c. the maximum allowable power dissipation is dictated by t j max, the junction-to-ambient thermal resistance ( ja ), and the ambient temperature (t a ), and can be calculated using the formula p d max = (t j max ? t a ) / ja . the values for maximum power dissipation listed above are reached only when the ADC141S628-Q1 is operated in a severe fault condition (for example, when input or output pins are driven beyond the power supply voltages, or the power- supply polarity is reversed). these conditions must be avoided. 6 specifications 6.1 absolute maximum ratings if military/aerospace specified devices are required, please contact the texas instruments sales office, distributors for availability and specifications. (1) (2) min max unit v a relative to gnd ? 0.3 6 v v io relative to gnd ? 0.3 6 v voltage between any two pins (3) 6 v current in or out of any pin (3) 10 ma package input current (3) 50 ma power consumption at t a = 25 c see (4) junction temperature 150 c storage temperature, t stg ? 65 150 c (1) aec q100-002 indicates that hbm stressing shall be in accordance with the ansi/esda/jedec js-001 specification. 6.2 esd ratings value unit v (esd) electrostatic discharge human-body model (hbm), per aec q100-002 (1) 4000 v charged-device model (cdm), per aec q100-011 1250 machine model (mm) 300 (1) all voltages are measured with respect to gnd = 0 v, unless otherwise specified. (2) for soldering specifications, see the absolute maximum ratings for soldering application report. 6.3 recommended operating conditions (1) (1) (2) min nom max unit operating temperature range ? 40 105 c supply voltage, v a 4.5 5.5 v supply voltage, v io 4.5 5.5 v reference voltage, v ref 1.0 v a v sclk frequency, f sclk 0.9 3.6 mhz analog input pin, +in gnd v a v analog input pin, ? in gnd 150 mv mv analog input voltage gnd v ref v digital input pins voltage range gnd v io v clock frequency 50k 3.6m hz
6 ADC141S628-Q1 snoi146c ? september 2011 ? revised december 2017 www.ti.com product folder links: ADC141S628-Q1 submit documentation feedback copyright ? 2011 ? 2017, texas instruments incorporated (1) typical values are at t j = 25 c and represent most likely parametric norms. test limits are specified to ti ' s average outgoing quality level (aoql). 6.4 ADC141S628-Q1 converter electrical characteristics the following specifications apply for v a = v io = 5 v, v ref = 4.096 v, and f sclk = 0.9 mhz to 3.6 mhz; f in = 20 khz and c l = 25 pf, unless otherwise noted. all specifications are at t a = 25 c, unless otherwise noted. (1) parameter test conditions min typ max unit static converter characteristics resolution with no missing codes t a = ? 40 c to +105 c 14 bits inl integral nonlinearity 0.5 lsb t a = ? 15 c to +65 c 0.95 t a = ? 40 c to +105 c 1 dnl differential nonlinearity 0.5 lsb t a = ? 40 c to +105 c 0.95 pctue post calibration total unadjusted error ? 15 c t a 65 c 0.5 mv ? 40 c t a 105 c ? 0.85 1 oe offset error ? 1 lsb t a = ? 40 c to +105 c 5 fse full-scale error ? 3 lsb t a = ? 40 c to +105 c 7 ge gain error ? 1.5 lsb t a = ? 40 c to +105 c 6 dynamic converter characteristics sinad signal-to-noise and distortion ratio v in = ? 0.1 dbfs 82 dbc v in = ? 0.1 dbfs, t a = ? 40 c to +105 c 80 snr signal-to-noise ratio v in = ? 0.1 dbfs 82 dbc v in = ? 0.1 dbfs, t a = ? 40 c to +105 c 80 thd total harmonic distortion v in = ? 0.1 dbfs ? 97 dbc sfdr spurious-free dynamic range v in = ? 0.1 dbfs 98 dbc enob effective number of bits v in = ? 0.1 dbfs 13.4 bits v in = ? 0.1 dbfs, t a = ? 40 c to +105 c 13.0 fpbw ? 3-db full-power bandwidth output at 70.7%fs with fs input, single-ended input 22 mhz analog input characteristics v in (+in) ? ( ? in) t a = ? 40 c to +105 c gnd v ref v +in noninverting input t a = ? 40 c to +105 c ? 0.15 v ref + 0.15 v ? in inverting input t a = ? 40 c to +105 c ? 0.15 0.15 v i dcl dc leakage current v in = v ref or v in = 0, t a = ? 40 c to +105 c 1 a c ina input capacitance in acquisition mode 14 pf in conversion mode 3.4 cmrr common-mode rejection ratio see the specification definitions section for the test condition 76 db
7 ADC141S628-Q1 www.ti.com snoi146c ? september 2011 ? revised december 2017 product folder links: ADC141S628-Q1 submit documentation feedback copyright ? 2011 ? 2017, texas instruments incorporated ADC141S628-Q1 converter electrical characteristics (continued) the following specifications apply for v a = v io = 5 v, v ref = 4.096 v, and f sclk = 0.9 mhz to 3.6 mhz; f in = 20 khz and c l = 25 pf, unless otherwise noted. all specifications are at t a = 25 c, unless otherwise noted. (1) parameter test conditions min typ max unit (2) the value of v io is independent of the value of v a . for example, v io can be operating at 5 v while v a is operating at 4.5 v or v io can be operating at 4.5 v while v a is operating at 5 v. digital input characteristics v ih input high voltage 1.9 v t a = ? 40 c to +105 c 2.3 v il input low voltage 1.0 v t a = ? 40 c to +105 c 0.7 i in input current v in = 0 v or v a , t a = ? 40 c to +105 c 1 a c ind input capacitance 2 pf t a = ? 40 c to +105 c 4 digital output characteristics v oh output high voltage i source = 200 a v a ? 0.05 v i source = 200 a, t a = ? 40 c to +105 c v a ? 0.2 i source = 1 ma v a ? 0.16 v ol output low voltage i sink = 200 a 0.01 v i sink = 200 a, t a = ? 40 c to +105 c 0.4 i sink = 1 ma 0.05 i ozh , i ozl tri-state leakage current force 0 v or v a , t a = ? 40 c to +105 c 1 a c out tri-state output capacitance force 0 v or v a 2 pf force 0 v or v a , t a = ? 40 c to +105 c 4 output coding straight binary power-supply characteristics v a analog supply voltage range t a = ? 40 c to +105 c 4.5 5.5 v v io digital input/output supply voltage range (2) t a = ? 40 c to +105 c 4.5 5.5 v v ref reference voltage range t a = ? 40 c to +105 c 1.0 v a v i va (conv) analog supply current, conversion mode f sclk = 3.6 mhz, f s = 200 ksps 740 a f sclk = 3.6 mhz, f s = 200 ksps, t a = ? 40 c to +105 c 970 i vio (conv) digital i/o supply current, conversion mode f sclk = 3.6 mhz, f s = 200 ksps 170 a f sclk = 3.6 mhz, f s = 200 ksps, t a = ? 40 c to +105 c 260 i vref (conv) reference current, conversion mode f sclk = 3.6 mhz, f s = 200 ksps 45 a f sclk = 3.6 mhz, f s = 200 ksps, t a = ? 40 c to +105 c 80 i va (pd) analog supply current, power-down mode ( cs high) f sclk = 3.6 mhz 8 a f sclk = low 2 f sclk = low, t a = ? 40 c to +105 c 3 i vio (pd) digital i/o supply current, power- down mode ( cs high) f sclk = 3.6 mhz 3 a f sclk = low 0.1 f sclk = low, t a = ? 40 c to +105 c 0.7
8 ADC141S628-Q1 snoi146c ? september 2011 ? revised december 2017 www.ti.com product folder links: ADC141S628-Q1 submit documentation feedback copyright ? 2011 ? 2017, texas instruments incorporated ADC141S628-Q1 converter electrical characteristics (continued) the following specifications apply for v a = v io = 5 v, v ref = 4.096 v, and f sclk = 0.9 mhz to 3.6 mhz; f in = 20 khz and c l = 25 pf, unless otherwise noted. all specifications are at t a = 25 c, unless otherwise noted. (1) parameter test conditions min typ max unit power-supply characteristics (continued) i vref (pd) reference current, power-down mode ( cs high) f sclk = 3.6 mhz 0.1 a f sclk = low 0.1 f sclk = low, t a = ? 40 c to +105 c 0.2 pwr (conv) power consumption, conversion mode f sclk = 3.6 mhz, f s = 200 ksps 4.8 mw f sclk = 3.6 mhz, f s = 200 ksps, t a = ? 40 c to +105 c 6.5 pwr (pd) power consumption, power-down mode ( cs high) f sclk = 0, v a = v io = v ref = 5.0 v 11 w f sclk = 0, v a = v io = v ref = 5.0 v, t a = ? 40 c to +105 c 19.5 psrr power-supply rejection ratio see the specification definitions section for the test condition ? 85 db ac electrical characteristics f sclk minimum clock frequency t a = ? 40 c to +105 c 3.6 0.9 mhz f s maximum sample rate t a = ? 40 c to +105 c 200 ksps t acq acquisition, track time t a = ? 40 c to +105 c 833 ns t conv conversion, hold time t a = ? 40 c to +105 c 15 sclk cycles t ad aperture delay see the specification definitions section 6 ns (1) typical values are at t j = 25 c and represent most likely parametric norms. test limits are specified to ti ' s average outgoing quality level (aoql). (2) t dis is the time for d out to change 10% while being loaded by the timing test circuit (see figure 2 ). 6.5 ADC141S628-Q1 timing requirements the following specifications apply for v a = v io = 5 v, v ref = 4.096 v, f sclk = 0.9 mhz to 3.6 mhz, and c l = 25 pf, unless otherwise noted. all specifications are at t a = 25 c, unless otherwise noted. (1) min nom max unit t css cs setup time prior to an sclk rising edge 3 ns (min) ? 40 c to +105 c 6 ns 1 / f sclk ? 3 ns (max) ? 40 c to +105 c 1 / f sclk ? 6 ns t dh d out hold time after an sclk falling edge 10 ns (min) ? 40 c to +105 c 6 ns t da d out access time after an sclk falling edge 28 ns (max) ? 40 c to +105 c 40 ns t dis d out disable time after the rising edge of cs (2) 10 ns (max) 20 ns t cs minimum cs pulse duration 5 ns (min) ? 40 c to +105 c 20 ns t en d out enable time after the falling edge of cs 32 ns (max) 51 ns t ch sclk high time ? 40 c to +105 c 111 ns t cl sclk low time ? 40 c to +105 c 111 ns t r d out rise time 7 ns t f d out fall time 7 ns
9 ADC141S628-Q1 www.ti.com snoi146c ? september 2011 ? revised december 2017 product folder links: ADC141S628-Q1 submit documentation feedback copyright ? 2011 ? 2017, texas instruments incorporated figure 1. ADC141S628-Q1 single conversion timing diagram figure 2. timing test circuit figure 3. d out rise and fall times figure 4. d out hold and access times figure 5. valid cs assertion times figure 6. voltage waveform for t dis 4 5 11 12 13 14 15 16 t acq (power-down) t conv (power-up) db13 db12 db5 db4 db3 db2 1 d ` sclk cs 2 3 17 18 0 0 0 1 db1 db0 2 t en t dis t cl t ch 0 t cs d out t f t r 0.9 x v io 0.1 x v io 1.6v to output pin cl 25 pf i oh i ol 2 ma 2 ma d out cs v ih t dis 90% 10% 90% 10% d out 90% 10% v il 2.3v 0.7v d out sclk t dh t da sclk cs t css 1 2
10 ADC141S628-Q1 snoi146c ? september 2011 ? revised december 2017 www.ti.com product folder links: ADC141S628-Q1 submit documentation feedback copyright ? 2011 ? 2017, texas instruments incorporated 6.6 typical characteristics v a = vio = v ref = 5 v, f sclk = 3.6 mhz, f sample = 200 ksps, t a = +25 c, and f in = 20 khz (unless otherwise noted) figure 7. dnl vs v a figure 8. inl vs v a figure 9. dnl vs v ref figure 10. inl vs v ref figure 11. dnl vs temperature figure 12. inl vs temperature -45 -25 -5 15 35 55 75 95 115 -1.0 -0.6 -0.2 0.2 0.6 1.0 inl (lsbs) temperature (c) max min va=2.7v va=3.6v va=5.5v -45 -25 -5 15 35 55 75 95 115 -1.0 -0.6 -0.2 0.2 0.6 1.0 dnl (lsbs) temperature (c) max min va=2.7v va=3.6v va=5.5v 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 3.0 3.5 4.0 4.5 5.0 v a (v) inl (lsbs) max min v ref = v a 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 2.0 3.0 4.0 5.0 6.0 v a (v) dnl (lsbs) max min v ref = v a 1 2 3 4 5 6 0.7 0.5 0.3 0.1 -0.1 -0.3 -0.5 -0.7 v ref (v) dnl (lsbs) max min v a =3v for v ref under 3v; v a =v ref otherwise
11 ADC141S628-Q1 www.ti.com snoi146c ? september 2011 ? revised december 2017 product folder links: ADC141S628-Q1 submit documentation feedback copyright ? 2011 ? 2017, texas instruments incorporated typical characteristics (continued) v a = vio = v ref = 5 v, f sclk = 3.6 mhz, f sample = 200 ksps, t a = +25 c, and f in = 20 khz (unless otherwise noted) figure 13. thd vs v a figure 14. sinad vs v a figure 15. thd vs temperature figure 16. sinad vs temperature figure 17. thd vs input frequency figure 18. sinad vs input frequency -45 -25 -5 15 35 55 75 95 115 70 75 80 85 90 sinad (db) temperature (c) va=vref=2.7v va=vref=3.6v va=vref=5.5v 0 10 20 30 40 50 60 70 80 90 100 input frequency (khz) sinad (db) 90 85 80 75 70 v ref = v a = v io = 5.5 -45 -25 -5 15 35 55 75 95 115 -120 -110 -100 -90 -80 thd (db) temperature (c) va = vref = 2.7v va = vref = 5.5v va = vref = 3.6v -80 -90 -100 -110 -120 0 10 20 30 40 50 60 70 80 90 100 input frequency (khz) thd (db) v a = v ref = v io = 5.5 2.5 3.0 3.5 4.0 4.5 5.0 5.5 90 85 80 75 70 v a (v) sinad (db) v ref = v a -80 -90 -100 -110 -120 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v a (v) thd (db) v a = v ref
12 ADC141S628-Q1 snoi146c ? september 2011 ? revised december 2017 www.ti.com product folder links: ADC141S628-Q1 submit documentation feedback copyright ? 2011 ? 2017, texas instruments incorporated typical characteristics (continued) v a = vio = v ref = 5 v, f sclk = 3.6 mhz, f sample = 200 ksps, t a = +25 c, and f in = 20 khz (unless otherwise noted) figure 19. gain and offset error vs temperature figure 20. gain and offset error vs v a figure 21. max tue vs temperature figure 22. min tue vs temperature figure 23. tue vs code over temperature figure 24. typical spectrum 0 20 40 60 80 100 -160 -140 -120 -100 -80 -60 -40 -20 0 magnitude (db) frequency (khz) -45 -25 -5 15 35 55 75 95 115 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 post calibration tue (lsbs) temperature (c) va=2.7v va=3.0v va=3.6v va=4.0v va=4.5v va=5.0v va=5.5v -45 -25 -5 15 35 55 75 95 115 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 post calibration tue (lsbs) temperature (c) va=2.7v va=3.0v va=3.6v va=4.0v va=4.5v va=5.0v va=5.5v 1.0 0.5 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 -45 -25 -5 15 35 55 75 95 115 temperature (c) error (lsbs) gain error offset error 1.0 0.5 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v a (v) error (lsbs) gain error v ref = v a = v io = 5.5 offset error 0 4096 8192 12288 16384 -1.0 -0.6 -0.2 0.2 0.6 1.0 tue (lsbs) output code -20c 25c 70c
13 ADC141S628-Q1 www.ti.com snoi146c ? september 2011 ? revised december 2017 product folder links: ADC141S628-Q1 submit documentation feedback copyright ? 2011 ? 2017, texas instruments incorporated typical characteristics (continued) v a = vio = v ref = 5 v, f sclk = 3.6 mhz, f sample = 200 ksps, t a = +25 c, and f in = 20 khz (unless otherwise noted) figure 25. v a current vs temperature figure 26. v a current vs v a figure 27. v io current vs temperature figure 28. v io current vs v io figure 29. v ref current vs temperature figure 30. v ref current vs v ref v a (v) i v a ( # a) 840 790 740 690 640 590 540 490 440 390 340 2.5 3.0 3.5 4.0 4.5 5.0 5.5 temperature (c) i vref ( # a) 17.0 16.5 16.0 15.5 15.0 -45 -25 -5 15 35 55 75 95 115 675 665 655 645 635 625 -45 -25 -5 15 35 55 75 95 115 temperature (c) i v a ( # a) v io (v) i v io ( # a) 252 194 136 78 20 2.5 3.0 3.5 4.0 4.5 5.0 5.5 temperature (c) i v io ( # a) 160 150 140 130 120 -45 -25 -5 15 35 55 75 95 115 v ref (v) i vref ( # a) 23 20 17 14 11 85 2 2.5 3.0 3.5 4.0 4.5 5.0 5.5
14 ADC141S628-Q1 snoi146c ? september 2011 ? revised december 2017 www.ti.com product folder links: ADC141S628-Q1 submit documentation feedback copyright ? 2011 ? 2017, texas instruments incorporated 7 detailed description 7.1 overview the ADC141S628-Q1 is a 14-bit, 200-ksps, sampling analog-to-digital converter (adc). the converter uses a successive-approximation register (sar) architecture based upon capacitive redistribution containing an inherent sample-and-hold function. the pseudo-differential nature of the analog inputs is maintained from the internal sample-and-hold circuits throughout the adc to provide excellent common-mode signal rejection. the ADC141S628-Q1 operates from independent analog and digital supplies. the analog supply (v a ) can range from 4.5 v to 5.5 v and the digital input/output supply (v io ) can range from 4.5 v to 5.5 v. the ADC141S628-Q1 uses an external reference (v ref ), which can be any voltage between 1 v and v a . the value of v ref determines the range of the analog input, while the reference input current (i ref ) depends upon the conversion rate. the analog input is presented across the two input pins: +in and ? in. the ? in pin is connected to the sensor ground in order to reject any small ground noise that is common to the +in and ? in. upon initiation of a conversion, the differential input is sampled on the internal capacitor array. the inputs are disconnected from the internal circuitry while a conversion is in progress. the ADC141S628-Q1 features a zero-power track mode where the adc is consuming the minimum amount of supply current while the internal sampling capacitor is tracking the applied analog input voltage. zero-power track mode starts after the 16th falling edge of the serial clock. the ADC141S628-Q1 communicates with other devices via a serial peripheral interface (spi) that operates using three pins: chip-select bar ( cs), serial clock (sclk), and serial data out (d out ). the external sclk controls data transfer and serves as the conversion clock. the duty cycle of sclk is essentially unimportant, provided the minimum clock high and low times are met. the minimum sclk frequency is set by internal capacitor leakage. each conversion requires 18 sclk cycles to complete. if less than 14 bits of conversion data are required, cs can be brought high at any point during the conversion. this procedure of terminating a conversion prior to completion is commonly referred to as short cycling. the digital conversion result is clocked out by the sclk input and is provided serially, most significant bit (msb) first, at the d out pin. the digital data that is provided at the d out pin is that of the conversion currently in progress and thus there is no pipe line delay. 7.2 feature description 7.2.1 reference input (v ref ) the externally supplied reference voltage (v ref ) sets the analog input range. the ADC141S628-Q1 will operate with v ref in the range of 1 v to v a . operation with v ref below 1 v is also possible with slightly diminished performance. as v ref is reduced, the range of acceptable analog input voltages is reduced. the peak-to-peak input range is limited to (v ref ). reducing v ref also reduces the size of the least significant bit (lsb). the size of one lsb is equal to [(v ref ) / 2n], where n is 14. when the lsb size goes below the noise floor of the ADC141S628-Q1, the noise spans an increasing number of codes and overall performance suffers. for example, the snr from dynamic signals degrades, while code uncertainty increases in dc measurements. because the noise is gaussian in nature, the effects of this noise can be reduced by averaging the results of a number of consecutive conversions. additionally, because offset and gain errors are specified in lsb, any offset or gain errors inherent in the adc increase in terms of lsb size as v ref is reduced. v ref and analog inputs (+in and ? in) are connected to the capacitor array through a switch matrix when the input is sampled. hence, i ref , i +in , and i ? in are a series of transient spikes that occur at a frequency dependent on the operating sample rate of the ADC141S628-Q1. i ref changes only slightly with temperature. see figure 29 for additional details.
15 ADC141S628-Q1 www.ti.com snoi146c ? september 2011 ? revised december 2017 product folder links: ADC141S628-Q1 submit documentation feedback copyright ? 2011 ? 2017, texas instruments incorporated feature description (continued) 7.2.2 analog signal inputs the ADC141S628-Q1 has a pseudo-differential input where the effective input voltage that is digitized is (+in) ? ( ? in) and ? in is restricted to be close to ground. by using this differential input, small signals common to both inputs are rejected. as shown in figure 31 , noise is rejected well at low frequencies where the common-mode rejection ratio (cmrr) is 90 db. as the frequency increases to 1 mhz, the cmrr rolls off to 40 db. figure 31. analog input cmrr vs frequency the current required to recharge the input sampling capacitor causes voltage spikes at +in and ? in. do not try to filter out these noise spikes. rather, ensure that the transients settle out during the acquisition period. 7.2.3 pseudo-differential operation for pseudo-differential operation, the noninverting input (+in) of the ADC141S628-Q1 can be driven with a signal that goes from gnd to a voltage equal to or less than v ref . connect the inverting input ( ? in) to either the local gnd or the remote sensor ground. this connection allows +in a maximum swing range of ground to v ref . figure 32 shows the ADC141S628-Q1 being driven by a full-scale single-ended source. figure 32. single-ended input + - a dc141s 628-q 1 c s src vref r s v ref 0v
16 ADC141S628-Q1 snoi146c ? september 2011 ? revised december 2017 www.ti.com product folder links: ADC141S628-Q1 submit documentation feedback copyright ? 2011 ? 2017, texas instruments incorporated feature description (continued) 7.2.4 serial digital interface the ADC141S628-Q1 communicates via a synchronous 3-wire serial interface as described in figure 1 or re- shown in figure 33 for convenience. cs, chip-select bar, initiates conversions and frames the serial data transfers. sclk (serial clock) controls both the conversion process and the timing of serial data. d out is the serial data output pin, where a conversion result is sent as a serial data stream, msb first. a serial frame is initiated on the falling edge of cs and ends on the rising edge of cs. the ADC141S628-Q1 d out pin is in a high-impedance state when cs is high and is active when cs is low; thus, cs acts as an output enable. the ADC141S628-Q1 samples the input upon the assertion of cs. assertion is defined as bringing the cs pin to a logic low state. for the first 15 periods of the sclk following the assertion of cs, the ADC141S628-Q1 is converting the analog input voltage. on the 16th falling edge of sclk, the ADC141S628-Q1 enters acquisition (t acq ) mode. for the next three periods of sclk, the ADC141S628-Q1 is operating in acquisition mode where the adc input is tracking the analog input signal applied across +in and ? in. during acquisition mode, the ADC141S628-Q1 is consuming a minimal amount of power. the ADC141S628-Q1 can enter conversion mode (t conv ) under three different conditions. the first condition involves cs going low (asserted) with sclk high. in this case, the ADC141S628-Q1 enters conversion mode on the first falling edge of sclk after cs is asserted. in the second condition, cs goes low with sclk low. under this condition, the ADC141S628-Q1 automatically enters conversion mode and the falling edge of cs is seen as the first falling edge of sclk. in the third condition, cs and sclk go low simultaneously and the adc141s628- q1 enters conversion mode. while there is no timing restriction with respect to the falling edges of cs and sclk, there is a minimum and maximum setup time requirements for the falling edge of cs with respect to the rising edge of sclk. see figure 5 for more information. figure 33. ADC141S628-Q1 single conversion timing diagram 7.2.5 cs input the cs (chip-select bar) input is active low and is ttl- and cmos-compatible. the ADC141S628-Q1 enters conversion mode when cs is asserted and the sclk pin is in a logic low state. when cs is high, the ADC141S628-Q1 is always in acquisition mode and thus consuming the minimum amount of power. because cs must be asserted to begin a conversion, the sample rate of the ADC141S628-Q1 is equal to the assertion rate of cs. proper operation requires that the fall of cs not occur simultaneously with a rising edge of sclk. if the fall of cs occurs during the rising edge of sclk, the data may be clocked out one bit early. whether or not the data are clocked out early depends upon how close the cs transition is to the sclk transition, the device temperature, and the characteristics of the individual device. to ensure that the msb is always clocked out at a given time (the third falling edge of sclk), the fall of cs must always meet the timing requirement specified in the ADC141S628-Q1 timing requirements table. 7.2.6 sclk input the sclk (serial clock) is used as the conversion clock to shift out the conversion result. sclk is ttl- and cmos-compatible. internal settling time requirements limit the maximum clock frequency while internal capacitor leakage limits the minimum clock frequency. the ADC141S628-Q1 offers specified performance with the clock rates indicated in the ADC141S628-Q1 converter electrical characteristics table. 4 5 11 12 13 14 15 16 t acq (power-down) t conv (power-up) db13 db12 db5 db4 db3 db2 1 d ` sclk cs 2 3 17 18 0 0 0 1 db1 db0 2 t en t dis t cl t ch 0 t cs
17 ADC141S628-Q1 www.ti.com snoi146c ? september 2011 ? revised december 2017 product folder links: ADC141S628-Q1 submit documentation feedback copyright ? 2011 ? 2017, texas instruments incorporated feature description (continued) the ADC141S628-Q1 enters acquisition mode on the 16th falling edge of sclk during a conversion frame. assuming that the lsb is clocked into a controller on the 16th rising edge of sclk, there is a minimum acquisition time period that must be met before a new conversion frame can begin. other than the 16th rising edge of sclk that was used to latch the lsb into a controller, there is no requirement for the sclk to transition during acquisition mode. therefore, sclk can be idle after the lsb is latched into the controller. 7.2.7 data output the data output format of the ADC141S628-Q1 is straight binary, as shown in figure 34 . this figure indicates the ideal output code for a given input voltage and does not include the effects of offset, gain error, linearity errors, or noise. each data output bit is output on the falling edges of sclk. the first and second sclk falling edges clock out leading zeros while the third to 16th sclk falling edges clock out the conversion result, msb first. figure 34. adc output vs input while most receiving systems capture the digital output bits on the rising edges of sclk, the falling edges of sclk may be used to capture the conversion result if the minimum hold time for d out is acceptable. see figure 4 for d out hold (t dh ) and access (t da ) times. d out is enabled on the falling edge of cs and disabled on the rising edge of cs. if cs is raised prior to the 16th falling edge of sclk, the current conversion is aborted and d out goes into its high impedance state. a new conversion begins when cs is driven low. 7.3 device functional modes 7.3.1 power consumption the architecture, design, and fabrication process allow the ADC141S628-Q1 to operate at conversion rates up to 200 ksps while consuming very little power. the ADC141S628-Q1 consumes the least amount of power while operating in acquisition (power-down) mode. for applications where power consumption is critical, operate the ADC141S628-Q1 in acquisition mode as often as the application tolerates. to further reduce power consumption, stop the sclk while cs is high. 7.3.1.1 short cycling short cycling refers to the process of halting a conversion after the last needed bit is outputted. short cycling can be used to lower the power consumption in those applications that do not need a full 14-bit resolution, or where an analog signal is being monitored until some condition occurs. in some circumstances, the conversion can be terminated after the first few bits. this termination lowers power consumption in the converter because the ADC141S628-Q1 spends more time in acquisition mode and less time in conversion mode. short cycling is accomplished by pulling cs high after the last required bit is received from the ADC141S628-Q1 output. this cycling is possible because the ADC141S628-Q1 places the latest converted data bit on d out as the bit is generated. if only 10-bits of the conversion result are needed, for example, the conversion can be terminated by pulling cs high after the 10th bit has been clocked out. | | | 11 1111 1111 1111 b 00 0000 0000 0000 b adc output code analog input +1 lsb +v ref - 1 lsb
18 ADC141S628-Q1 snoi146c ? september 2011 ? revised december 2017 www.ti.com product folder links: ADC141S628-Q1 submit documentation feedback copyright ? 2011 ? 2017, texas instruments incorporated device functional modes (continued) 7.3.1.2 burst mode operation normal operation of the ADC141S628-Q1 requires the sclk frequency to be 18 times the sample rate and the cs rate to be the same as the sample rate. however, in order to minimize power consumption in applications requiring sample rates below 200 ksps, run the ADC141S628-Q1 with an sclk frequency of 3.6 mhz and a cs rate as slow as the system requires. when this set up is accomplished, the ADC141S628-Q1 operates in burst mode. the ADC141S628-Q1 enters into acquisition mode at the end of each conversion, minimizing power consumption, which causes the converter to spend the longest possible time in acquisition mode. because power consumption scales directly with conversion rate, minimizing power consumption requires determining the lowest conversion rate that will satisfy the requirements of the system. 8 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 8.1 application information 8.1.1 application circuits the following figure is an example of the ADC141S628-Q1 in a typical application circuit. this circuit is basic and generally requires modification for specific circumstances. 8.1.1.1 data acquisition figure 35 shows a typical connection diagram for the ADC141S628-Q1 operating at v a of 5 v. v ref is connected to a 4.1-v shunt reference, the lm4040-4.1, to define the analog input range of the ADC141S628-Q1 independent of supply variation on the 5-v supply line. decouple the v ref pin to the ground plane by a 0.1- f ceramic capacitor and a tantalum capacitor of 10 f. the 0.1- f capacitor must be placed as close as possible to the v ref pin while the placement of the tantalum capacitor is less critical. the v a and v io pins of the ADC141S628-Q1 are also recommended to be decoupled to ground by a 0.1- f ceramic capacitor in parallel with a 10- f tantalum capacitor. figure 35. low-cost, low-power data acquisition system 100 : + adc141s628 -q1 v ref +in - in gnd v a sclk d out csb 0.1 p f 10 p f 0.1 p f + 10 p f +5v controller lm4040 -4.1 v io
19 ADC141S628-Q1 www.ti.com snoi146c ? september 2011 ? revised december 2017 product folder links: ADC141S628-Q1 submit documentation feedback copyright ? 2011 ? 2017, texas instruments incorporated 9 power supply recommendations 9.1 analog and digital power supplies any adc architecture is sensitive to spikes on the power supply, reference, and ground pins. these spikes may originate from switching power supplies, digital logic, high power devices, and other sources. power to the ADC141S628-Q1 must be clean and well bypassed. use a 0.1- f ceramic bypass capacitor and a 1- f to 10- f capacitor to bypass the ADC141S628-Q1 supply, with the 0.1- f capacitor placed as close to the adc141s628- q1 package as possible. because the ADC141S628-Q1 has both the v a and v io pins, the user has three options on how to connect these pins. the first option is to tie v a and v io together and power them with the same power supply. this connection is the most cost effective way of powering the ADC141S628-Q1 but is also the least ideal. as stated previously, noise from v io can couple into v a and adversely affect performance. the other two options involve the user powering v a and v io with separate supply voltages. these supply voltages can have the same amplitude or they can be different. these voltages may be set independent of each other and can be any value between 4.5 v and 5.5 v. best performance is typically achieved with v a operating at 5 v. operating v a at 5 v offers the best linearity and dynamic performance when v ref is also set to 5 v. 9.2 voltage reference the reference source must have a low output impedance and must be bypassed with a minimum capacitor value of 0.1 f. a larger capacitor value of 1 f to 10 f placed in parallel with the 0.1- f capacitor is preferred. while the ADC141S628-Q1 draws very little current from the reference on average, there are higher instantaneous current spikes at the reference. the v ref of the ADC141S628-Q1, like all adcs, does not reject noise or voltage variations. keep this fact in mind if v ref is derived from the power supply. any noise or ripple from the supply that is not rejected by the external reference circuitry appears in the digital results. the use of an active reference source is recommended. the lm4040 and lm4050 shunt reference families and the lm4132 and lm4140 series reference families are excellent choices for a reference source.
20 ADC141S628-Q1 snoi146c ? september 2011 ? revised december 2017 www.ti.com product folder links: ADC141S628-Q1 submit documentation feedback copyright ? 2011 ? 2017, texas instruments incorporated 10 layout 10.1 layout guidelines for best performance, care must be taken with the physical layout of the printed circuit board, which is especially true with a low v ref or when the conversion rate is high. at high clock rates there is less time for settling, so any noise must settle out before the conversion begins. 10.1.1 pcb layout capacitive coupling between the noisy digital circuitry and the sensitive analog circuitry can lead to poor performance. the solution is to keep the analog circuitry separated from the digital circuitry and the clock line as short as possible. digital circuits create substantial supply and ground current transients. the logic noise generated can have significant impact upon system noise performance. to avoid performance degradation of the ADC141S628-Q1 because of supply noise, avoid using the same supply for the v a and v ref of the ADC141S628-Q1 that is used for digital circuitry on the board. generally, analog and digital lines must cross each other at 90 to avoid crosstalk. however, to maximize accuracy in high resolution systems, avoid crossing analog and digital lines altogether. clock lines must be kept as short as possible and isolated from all other lines, including other digital lines. in addition, the clock line must also be treated as a transmission line and be properly terminated. isolate the analog input from noisy signal traces to avoid coupling of spurious signals into the input. any external component (for example, a filter capacitor) connected between the converter input pins and ground or to the reference input pin and ground must be connected to a very clean point in the ground plane. a single, uniform ground plane and the use of split power planes are recommended. place the power planes within the same board layer. all analog circuitry (input amplifiers, filters, reference components, and so forth) must be placed over the analog power plane. place all digital circuitry over the digital power plane. furthermore, the gnd pins on the ADC141S628-Q1 and all the components in the reference circuitry and input signal chain that are connected to ground must be connected to the ground plane at a quiet point. avoid connecting these points too close to the ground point of a microprocessor, microcontroller, digital signal processor, or other high power digital device.
21 ADC141S628-Q1 www.ti.com snoi146c ? september 2011 ? revised december 2017 product folder links: ADC141S628-Q1 submit documentation feedback copyright ? 2011 ? 2017, texas instruments incorporated 11 device and documentation support 11.1 device support 11.1.1 device nomenclature 11.1.1.1 specification definitions aperture delay is the time between the first falling edge of sclk and the time when the input signal is sampled for conversion. common-mode rejection ratio (cmrr) is a measure of how well in-phase signals common to both input pins are rejected. to calculate cmrr, the change in output offset is measured while the common mode input voltage is changed from 2 v to 3 v. cmrr = 20 log ( common input / output offset) (1) conversion time is the time required, after the input voltage is acquired, for the adc to convert the input voltage to a digital word. differential nonlinearity (dnl) is the measure of the maximum deviation from the ideal step size of 1 lsb. duty cycle is the ratio of the time that a repetitive digital waveform is high to the total time of one period. the specification here refers to the sclk. effective number of bits (enob, or effective bits) is another method of specifying signal-to-noise and distortion or sinad. enob is defined as (sinad ? 1.76) / 6.02 and says that the converter is equivalent to a perfect adc of this (enob) number of bits. full power bandwidth is a measure of the frequency at which the reconstructed output fundamental drops 3 db below its low frequency value for a full-scale input. full-scale error is the difference between the input voltage at which the output code transitions to positive full-scale and v ref minus 1 lsb. gain error is the deviation from the ideal slope of the transfer function. gain error is the difference between positive full-scale error and negative full-scale error and can be calculated as: gain error = positive full-scale error ? negative full-scale error (2) integral nonlinearity (inl) is a measure of the deviation of each individual code from a line drawn from ? lsb below the first code transition through ? lsb above the last code transition. the deviation of any given code from this straight line is measured from the center of that code value. missing codes are those output codes that will never appear at the adc outputs. the ADC141S628-Q1 is specified not to have any missing codes. offset error is the difference between the input voltage at which the output code transitions from code 0000h to 0001h and 1 lsb. post calibration total unadjusted error is the total unadjusted error over the temperature range after system calibration to remove gain and offset errors at 25 c. power-supply rejection ratio (psrr) is a measure of how well a change in the analog supply voltage is rejected. psrr is calculated from the ratio of the change in offset error for a given change in supply voltage, expressed in db. for the ADC141S628-Q1, v a is changed from 4.5 v to 5.5 v. psrr = 20 log ( output offset / v a ) (3) signal-to-noise ratio (snr) is the ratio, expressed in db, of the rms value of the input signal to the rms value of the sum of all other spectral components below one-half the sampling frequency, not including harmonics or dc. signal-to-noise and distortion (s/n+d or sinad) is the ratio, expressed in db, of the rms value of the input signal to the rms value of all of the other spectral components below one-half the sampling frequency, including harmonics but excluding dc.
22 ADC141S628-Q1 snoi146c ? september 2011 ? revised december 2017 www.ti.com product folder links: ADC141S628-Q1 submit documentation feedback copyright ? 2011 ? 2017, texas instruments incorporated device support (continued) spurious-free dynamic range (sfdr) is the difference, expressed in db, between the desired signal amplitude to the amplitude of the peak spurious spectral component below one-half the sampling frequency, where a spurious spectral component is any signal present in the output spectrum that is not present at the input and may or may not be a harmonic. total harmonic distortion (thd) is the ratio of the rms total of the first five harmonic components at the output to the rms level of the input signal frequency as seen at the output, expressed in db. thd is calculated as: where ? a f1 is the rms power of the input frequency at the output ? a f2 through a f6 are the rms power in the first five harmonic frequencies (4) total unadjusted error is the difference between the parts transfer function and the ideal transfer function. throughput time is the minimum time required between the start of two successive conversion. 11.2 documentation support 11.2.1 related documentation for related documentation see the following: ? lm4040xxx precision micropower shunt voltage reference ? lm4050-n/-q1 precision micropower shunt voltage reference ? lm4132, lm4132-q1 sot-23 precision low dropout voltage reference ? lm4140 high precision low noise low dropout voltage reference ? absolute maximum ratings for soldering 11.3 receiving notification of documentation updates to receive notification of documentation updates, navigate to the device product folder on ti.com. in the upper right corner, click on alert me to register and receive a weekly digest of any product information that has changed. for change details, review the revision history included in any revised document. 11.4 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 11.5 trademarks e2e is a trademark of texas instruments. spi, qspi are trademarks of motorola mobility llc. all other trademarks are the property of their respective owners. 11.6 electrostatic discharge caution this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 2 1f 2 6f 2 2f 10 ? a a+ + a log 20= thd "
23 ADC141S628-Q1 www.ti.com snoi146c ? september 2011 ? revised december 2017 product folder links: ADC141S628-Q1 submit documentation feedback copyright ? 2011 ? 2017, texas instruments incorporated 11.7 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. 12 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation.
package option addendum www.ti.com 21-dec-2017 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples adc141s628qimm/nopb active vssop dgs 10 1000 green (rohs & no sb/br) cu sn level-1-260c-unlim -40 to 105 x96q adc141s628qimmx/nopb active vssop dgs 10 3500 green (rohs & no sb/br) cu sn level-1-260c-unlim -40 to 105 x96q (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) rohs: ti defines "rohs" to mean semiconductor products that are compliant with the current eu rohs requirements for all 10 rohs substances, including the requirement that rohs substance do not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, "rohs" products are suitable for use in specified lead-free processes. ti may reference these types of products as "pb-free". rohs exempt: ti defines "rohs exempt" to mean products that contain lead but are compliant with eu rohs pursuant to a specific eu rohs exemption. green: ti defines "green" to mean the content of chlorine (cl) and bromine (br) based flame retardants meet js709b low halogen requirements of <=1000ppm threshold. antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
package option addendum www.ti.com 21-dec-2017 addendum-page 2
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant adc141s628qimm/nop b vssop dgs 10 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 q1 adc141s628qimmx/no pb vssop dgs 10 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 q1 package materials information www.ti.com 22-dec-2017 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) adc141s628qimm/nopb vssop dgs 10 1000 210.0 185.0 35.0 adc141s628qimmx/nop b vssop dgs 10 3500 367.0 367.0 35.0 package materials information www.ti.com 22-dec-2017 pack materials-page 2

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